{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1554625955666 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1554625955674 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 07 16:32:35 2019 " "Processing started: Sun Apr 07 16:32:35 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1554625955674 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1554625955674 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Trigger -c Trigger " "Command: quartus_map --read_settings_files=on --write_settings_files=off Trigger -c Trigger" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1554625955674 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1554625958462 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Analysis & Synthesis" 0 -1 1554625958462 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mysynchro.v 1 1 " "Found 1 design units, including 1 entities, in source file mysynchro.v" { { "Info" "ISGN_ENTITY_NAME" "1 mysynchro " "Found entity 1: mysynchro" {  } { { "mysynchro.v" "" { Text "E:/My_design/Trigger/mysynchro.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1554625991350 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1554625991350 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myasynchro.v 1 1 " "Found 1 design units, including 1 entities, in source file myasynchro.v" { { "Info" "ISGN_ENTITY_NAME" "1 myasynchro " "Found entity 1: myasynchro" {  } { { "myasynchro.v" "" { Text "E:/My_design/Trigger/myasynchro.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1554625991356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1554625991356 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trigger.v 1 1 " "Found 1 design units, including 1 entities, in source file trigger.v" { { "Info" "ISGN_ENTITY_NAME" "1 Trigger " "Found entity 1: Trigger" {  } { { "Trigger.v" "" { Text "E:/My_design/Trigger/Trigger.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1554625991366 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1554625991366 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Trigger " "Elaborating entity \"Trigger\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1554625991414 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myasynchro myasynchro:G " "Elaborating entity \"myasynchro\" for hierarchy \"myasynchro:G\"" {  } { { "Trigger.v" "G" { Text "E:/My_design/Trigger/Trigger.v" 6 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1554625991417 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mysynchro mysynchro:F " "Elaborating entity \"mysynchro\" for hierarchy \"mysynchro:F\"" {  } { { "Trigger.v" "F" { Text "E:/My_design/Trigger/Trigger.v" 7 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1554625991419 ""}
{ "Warning" "WMLS_MLS_CREATED_ALOAD_CCT" "" "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "mysynchro:F\|out_lock2 mysynchro:F\|out_lock2~_emulated mysynchro:F\|out_lock2~1 " "Register \"mysynchro:F\|out_lock2\" is converted into an equivalent circuit using register \"mysynchro:F\|out_lock2~_emulated\" and latch \"mysynchro:F\|out_lock2~1\"" {  } { { "mysynchro.v" "" { Text "E:/My_design/Trigger/mysynchro.v" 4 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Design Software" 0 -1 1554625992114 "|Trigger|mysynchro:F|out_lock2"}  } {  } 0 13004 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "Analysis & Synthesis" 0 -1 1554625992114 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1554625992371 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1554625992801 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1554625992801 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1554625992834 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1554625992834 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5 " "Implemented 5 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1554625992834 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1554625992834 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4816 " "Peak virtual memory: 4816 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1554625992843 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 07 16:33:12 2019 " "Processing ended: Sun Apr 07 16:33:12 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1554625992843 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1554625992843 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1554625992843 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1554625992843 ""}